基于单片机的外文文献翻译

范文一：基于单片机的外文文献翻译

本科毕业设计（论文）

AT89S52单片机应用中英文翻译

专业名称：电气工程及其自动化

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河南理工大学电气学院

二O一二年六月九日

AT89S52 MCU Applications

Function Characteristic Description

The AT89S52 is a low-power, high-performance CMOS 8-bit microcontroller with 8K bytes of in-system programmable Flash memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the indus-try-standard 80C51 instruction set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory pro-grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on a monolithic chip, the Atmel AT89S52 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications.The AT89S52 provides the following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down mode saves the RAM con-tents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.

Pin Description

VCC ：Supply voltage.

GND ：Ground.

Port 0：Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur-ing program verification. External pull-ups are required during program verification.

Port 1：Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output

buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the follow-ing table 1. Port 1 also receives the low-order address bytes during Flash programming and verification.

Port 2：Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and dur-ing accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash program-ming and verification.

Port 3：Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter-nal pull-ups and can be used as inputs. As inputs, Port 3 pins that are

externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89S52, as shown in the fol-lowing table 2.

RST：Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives high for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.

ALE/PROG：Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dur-ing each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

PSEN：Program Store Enable (PSEN) is the read strobe to external program memory. When the AT89S52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each

access to exter-nal data memory.

EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming.

XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2：Output from the inverting oscillator amplifier.

Program Memory

If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89S52, if EA is connected to VCC, program fetches to addresses 0000H through 1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are to external memory.

Data Memory

The AT89S52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. This means that the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions which use direct addressing access the SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2). MOV 0A0H, #data. Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).MOV @R0, #data. Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.

Watchdog Timer

The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over-flows, it will drive an output RESET HIGH pulse at the RST pin.

In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89S52 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode. To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down mode. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89S52 while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode. With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.

Timer 0 and 1

Timer 0 and Timer 1 in the AT89S52 operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information on the timers’ operation, please click on the document link below: Timer 2

Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON. Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 6-1. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscil-lator frequency.

In the Counter function, the register is incremented in response to a 1-to-0 transition at its corre-sponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.

Interrupts The AT89S52 has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that bit position IE.6 is unimplemented. User software should not write a 1 to this bit position, since it may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Nei-ther of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven,. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clock-ing circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.

Power-down Mode

In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down mode can be initiated either by a hardware reset or by an enabled external interrupt. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held

active long enough to allow the oscillator to restart and stabilize.

Idle Mod

In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions regis-ters remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-gram execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory.

AT89S52单片机应用

功能特征描述

AT89S52是一种低功耗、高性能CMOS8位微控制器，具有8K 在系统可编程Flash 存储器。使用Atmel 公司高密度非易失性存储器技术制造，与工业80C51 产品指令和引脚完全兼容。片上Flash允许程序存储器在系统可编程，亦适于常规编程器。在单芯片上，拥有灵巧的8 位CPU 和在系统可编程Flash，使得AT89S52为众多嵌入式控制应用系统提供高灵活、超有效的解决方案。 AT89S52具有以下标准功能： 8k字节Flash，256字节RAM，32 位I/O 口线，看门狗定时器，2个数据指针，三个16 位定时器/计数器，一个6向量2级中断结构，全双工串行口，片内晶振及时钟电路。另外，AT89S52 可降至0Hz 静态逻辑操作，支持2种软件可选择节电模式。空闲模式下，CPU停止工作，允许RAM、定时器/计数器、串口、中断继续工作。掉电保护方式下，RAM内容被保存，振荡器被冻结，单片机一切工作停止，直到下一个中断或硬件复位为止。

引脚描述

VCC ：电源。

GND: 接地。

P0口： P0口是一个8位漏极开路的双向I/O口。作为输出口，每位能驱动8个TTL逻辑电平。对P0端口写“1”时，引脚用作高阻抗输入。当访问外部程序和数据存储器时，P0口也被作为低8位地址/数据复用。在这种模式下，P0具有内部上拉电阻。在flash编程时，P0口也用来接收指令字节；在程序校验时，输出指令字节。程序校验时，需要外部上拉电阻。

P1口：P1 口是一个具有内部上拉电阻的8 位双向I/O 口，p1 输出缓冲器能驱动4 个TTL 逻辑电平。对P1 端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（IIL）。此外，P1.0和P1.2分别作定时器/计数器2的外部计数输入（P1.0/T2）和时器/计数器2的触发输入（P1.1/T2EX），具体如下表1所示。在flash编程和校验时，P1口接收低8位地址字节。

P2口：P2 口是一个具有内部上拉电阻的8 位双向I/O 口，P2 输出缓冲器能驱动4 个TTL 逻辑电平。对P2 端口写“1”时，内部上拉电阻把端口拉高，此时可以

作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电（IIL）。在访问外部程序存储器或用16位地址读取外部数据存储器（例如执行MOVX @DPTR）时，P2 口送出高八位地址。在这种应用中，P2 口使用很强的内部上拉发送1。在使用8位地址（如MOVX @RI）访问外部数据存储器时，P2口输出P2锁存器的内容。在flash编程和校验时，P2口也接收高8位地址字节和一些控制信号。

表1 P1口第二功能

表2 P3口第二功能

P3口：P3 口是一个有内部上拉电阻的8 位双向I/O 口，p2 输出缓冲器能驱动4 个TTL 逻辑电平。对P3 端口写“1”时，内部上拉电阻把端口拉高，此时可以作为输入口使用。作为输入使用时，被外部拉低的引脚由于内部电阻的原因，将输出电流（IIL）。P3口亦作为AT89S52特殊功能（第二功能）使用，如2表所示。在flash

编程和校验时，P3口也接收一些控制信号。

RST：复位输入。晶振工作时，RST脚持续2 个机器周期高电平将使单片机复位。看门狗计时完成后，RST 脚输出96 个晶振周期的高电平。特殊寄存器AUXR(地址8EH)上的DISRTO位可以使此功能无效。DISRTO默认状态下，复位高电平有效。 ALE/PROG：地址锁存控制信号（ALE）是访问外部程序存储器时，锁存低8 位地址的输出脉冲。在flash编程时，此引脚(PROG)也用作编程输入脉冲。在一般情况下，ALE 以晶振六分之一的固定频率输出脉冲，可用来作为外部定时器或时钟使用。然而，特别强调，在每次访问外部数据存储器时，ALE脉冲将会跳过。如果需要，通过将地址为8EH的SFR的第0位置 “1”，ALE操作将无效。这一位置 “1”，ALE 仅在执行MOVX 或MOVC指令时有效。否则，ALE 将被微弱拉高。这个ALE 使能标志位（地址为8EH的SFR的第0位）的设置对微控制器处于外部执行模式下无效。

PSEN：外部程序存储器选通信号(PSEN)是外部程序存储器选通信号。当AT89S52从外部程序存储器执行外部代码时，PSEN在每个机器周期被激活两次，而在访问外部数据存储器时，PSEN将不被激活。

EA/VPP：访问外部程序存储器控制信号。为使能从0000H 到FFFFH的外部程序存储器读取指令，EA必须接GND。为了执行内部程序指令，EA应该接VCC。在flash编程期间，EA也接收12伏VPP电压。

XTAL1：振荡器反相放大器和内部时钟发生电路的输入端。

XTAL2：振荡器反相放大器的输出端。

程序存储器如果EA引脚接地，程序读取只从外部存储器开始。对于89S52，如果EA 接VCC，程序读写先从内部存储器（地址为0000H～1FFFH）开始，接着从外部寻址，寻址地址为：2000H~FFFFH。

数据存储器

AT89S52 有256 字节片内数据存储器。高128 字节与特殊功能寄存器重叠。也就是说高128字节与特殊功能寄存器有相同的地址，而物理上是分开的。当一条指令访问高于7FH 的地址时，寻址方式决定CPU 访问高128 字节RAM 还是特殊功能寄存器空间。直接寻址方式访问特殊功能寄存器（SFR）。例如，下面的直接寻址指令访问0A0H（P2口）存储单元MOV 0A0H , #data。使用间接寻址方式访问高128 字节

RAM。例如，下面的间接寻址方式中，R0 内容为0A0H，访问的是地址0A0H的寄存器，而不是P2口（它的地址也是0A0H）。MOV @R0 , #data。堆栈操作也是简介寻址方式。因此，高128字节数据RAM也可用于堆栈空间。

看门狗定时器

WDT是一种需要软件控制的复位方式。WDT 由13位计数器和特殊功能寄存器中的看门狗定时器复位存储器（WDTRST）构成。WDT 在默认情况下无法工作；为了激活WDT，户用必须往WDTRST 寄存器（地址：0A6H）中依次写入01EH 和0E1H。当WDT激活后，晶振工作，WDT在每个机器周期都会增加。WDT计时周期依赖于外部时钟频率。除了复位（硬件复位或WDT溢出复位），没有办法停止WDT工作。当WDT溢出，它将驱动RSR引脚一个高个电平输出。

在掉电模式下，晶振停止工作，这意味这WDT也停止了工作。在这种方式下，用户不必喂狗。有两种方式可以离开掉电模式：硬件复位或通过一个激活的外部中断。通过硬件复位退出掉电模式后，用户就应该给WDT 喂狗，就如同通常AT89S52 复位一样。通过中断退出掉电模式的情形有很大的不同。中断应持续拉低很长一段时间，使得晶振稳定。当中断拉高后，执行中断服务程序。为了防止WDT在中断保持低电平的时候复位器件，WDT 直到中断拉低后才开始工作。这就意味着WDT 应该在中断服务程序中复位。为了确保在离开掉电模式最初的几个状态WDT不被溢出，最好在进入掉电模式前就复WDT。在进入待机模式前，特殊寄存器AUXR的WDIDLE位用来决定WDT是否继续计数。默认状态下，在待机模式下，WDIDLE＝0，WDT继续计数。为了防止WDT在待机模式下复位AT89S52，用户应该建立一个定时器，定时离开待机模式，喂狗，再重新进入待机模式。

定时器0和定时器1

在AT89S52 中，定时器0 和定时器1 的操作与AT89C51 和AT89C52 一样。为了获得更深入的关于UART 的信息，可参考ATMEL 网站（http://www.atmel.com）。从这个主页，选择“Products”，然后选择“8051-Architech Flash Microcontroller”，再选择“Product Overview”即可。

定时器2

定时器2是一个16位定时/计数器，它既可以做定时器，又可以做事件计数器。

其工作方式由特殊寄存器T2CON中的C/T2位选择（如表2所示）。定时器2有三种工作模式：捕捉方式、自动重载（向下或向上计数）和波特率发生器。如表3 所示，工作模式由T2CON中的相关位选择。定时器2 有2 个8位寄存器：TH2和TL2。在定时工作方式中，每个机器周期，TL2 寄存器都会加1。由于一个机器周期由12 个晶振周期构成，因此，计数频率就是晶振频率的1/12。

表3 定时器2工作模式

在计数工作方式下，寄存器在相关外部输入角T2 发生1 至0 的下降沿时增加1。在这种方式下，每个机器周期的S5P2期间采样外部输入。一个机器周期采样到高电平，而下一个周期采样到低电平，计数器将加1。在检测到跳变的这个周期的S3P1 期间，新的计数值出现在寄存器中。因为识别1－0的跳变需要2个机器周期（24个晶振周期），所以，最大的计数频率不高于晶振频率的1/24。为了确保给定的电平在改变前采样到一次，电平应该至少在一个完整的机器周期内保持不变。

中断

AT89S52 有6个中断源：两个外部中断（INT0 和INT1），三个定时中断（定时器0、1、2）和一个串行中断。每个中断源都可以通过置位或清除特殊寄存器IE 中的相关中断允许控制位分别使得中断源有效或无效。IE还包括一个中断允许总控制位EA，它能一次禁止所有中断。IE.6位是不可用的。对于AT89S52，IE.5位也是不能用的。用户软件不应给这些位写1。它们为AT89系列新产品预留。定时器2可以被寄存器T2CON中的TF2和EXF2的或逻辑触发。程序进入中断服务后，这些标志位都可以由硬件清0。实际上，中断服务程序必须判定是否是TF2 或EXF2激活中断，标志位也必须由软件清0。定时器0和定时器1标志位TF0 和TF1在计数溢出的那个周期的S5P2被置位。它们的值一直到下一个周期被电路捕捉下来。然而，定时器2 的标志位TF2 在计数溢出的那个周期的S2P2被置位，在同一个周期被电路捕捉下来。

晶振特性

AT89S52 单片机有一个用于构成内部振荡器的反相放大器，XTAL1 和XTAL2 分别是放大器的输入、输出端。石英晶体和陶瓷谐振器都可以用来一起构成自激振荡器。从外部时钟源驱动器件的话，XTAL2 可以不接，而从XTAL1 接入。由于外部时钟信号经过二分频触发后作为外部时钟电路输入的，所以对外部时钟信号的占空比没有其它要求，最长低电平持续时间和最少高电平持续时间等还是要符合要求的。掉电模式

在掉电模式下，晶振停止工作，激活掉电模式的指令是最后一条执行指令。片上RAM和特殊功能寄存器保持原值，直到掉电模式终止。掉电模式可以通过硬件复位和外部中断退出。复位重新定义了SFR 的值，但不改变片上RAM 的值。在VCC未恢复到正常工作电压时，硬件复位不能无效，并且应保持足够长的时间以使晶振重新工作和初始化。

空闲模式

在空闲工作模式下，CPU 处于睡眠状态，而所有片上外部设备保持激活状态。这种状态可以通过软件产生。在这种状态下，片上RAM和特殊功能寄存器的内容保持不变。空闲模式可以被任一个中断或硬件复位终止。由硬件复位终止空闲模式只需两个机器周期有效复位信号，在这种情况下，片上硬件禁止访问内部RAM，而可以访问端口引脚。空闲模式被硬件复位终止后，为了防止预想不到的写端口，激活空闲模式的那一条指令的下一条指令不应该是写端口或外部存储器。

范文二：8单片机外文翻译外文文献英文文献基于单片机的电动智能小车

基于单片机的电动智能小车

通过研发实现了一种以光电传感器为敏感元件，以 AT89C51 单片机为控制核心的电动循迹小车的智能控，该系统还包括直流电机、L9110 芯片和 LM324 比较器等。本设计采用 AT89C51 单片机作为智能小车核心控制器。

本系统以单片机为控制核心 ,实现电动车的前进、退、左转和右转功能.通过角度传感器 [ 1 ]检测跷跷板角度的变化 ,利用增量式 PI算法 [ 2 ]控制电动车寻找平衡点 ,同时运用光电传感器检测黑线 ,使电动车在行驶过程中保持直线运动且不会脱离跷跷。

一(方案设计

电动车的速度、位置、运行状况的实时测量，并将测量数据传送至单片机进行处理，然后由单片机根据所检测的各种数据实现对电动车的智能控制。这种方案能实现对电动车的运动状态进行实时控制，控制，灵活可靠，精度高，可满足对系统的各项要求。(1)直流调速系统直流调速系统采用脉宽调速系统，其主电路采用脉宽调制式变换器，简称PWM变换器。由于PWM调速系统的开关频率较高，仅靠电枢电感的滤波作用就可以获得脉动很小的直流电流，电枢电流容易连续，系统的低速运行平稳，调速范围较宽，可达1:10000左右。由于电流波形比 V-M系统好，在相同的平均电流下，电动机的损耗和发热都比较小。同样由于开关频率高，若与快速响应的电机相配合，系统可以获得很宽的频带，因此快速响应性能好，动态抗扰能力强。根据以上综合比较，以及本设计中受控电机的容量和直流电机调速的发展方向，本设计采用了H型单极型可逆 PWM变换器进行调速。

1.1 光电检测模块设计

该智能小车在贴有黑线的白纸“路面”上行驶，因此本模块设计需要检测铺在行驶区的黑胶带，包括直线行驶区和沿弧线行驶区两个区域。由于黑线和白纸对光线的反射系数不同可根据接收到的反射光的强弱来判断“道路”---黑线。本文采用的是简单实用的检测方法，即红外探测法。

红外探测法，即利用红外线在不同颜色的物理表面具有不同的反射性质的特点。在小车行驶过程中不断地向地面发射红外光，当红外光遇到白色地面时发生漫发射，反射光被装在小车上的接收管接收; 如果遇到黑线则红外光被吸收，则小车上的接收管接收不到信号。

1.2 信号比较模块设计

输送给单片机，用于检测传感器的敏感性，电路图如图 5 所示。当两个传感器同时检测到光时，直线前进。当传感器检测不到光时，处于截止状态，双运算放大器 LM324 输出低电平给单片机，由程序处理; 若左路未检测到光，则向左纠正方向; 若右路未检测到光，则向右纠正方向。

1.3 电机控制与驱动模块设计

由于采用的是双驱动的小车，这部分电路必须能够输出两个不同的电压值，分别去控制小车的左、右两个驱动电机，使小车的两个车轮的转速和方向相同或不同，从而来控制它的前进和转弯。在系统的设计过程中，用两个 L9110 芯片来分别连接单片机和直流电机。L9110 是为控制和驱动电机设计的两通道推挽式功率放大专用集成电路器件，将分立电路集成在单片 IC 之中，使外围器件成本降低，整机可靠性提高。该芯片有两个 TTL / CMOS 兼容电平的输入，具

有良好的抗干扰性; 两个输出端能直接驱动电机的正反向运动，它具有较大的电流驱动能力，每通道能通过800mA 的持续电流，峰值电流能力可达 1.5 , 2.0A; 同时它具有较低的输出饱和压降与静态电流; 内置的钳位二极管能释放感性负载的反向冲击电流，使它在驱动继电器、直流电机、步进电机或开关功率管的使用上安全可靠。

循迹小车系统以常见的 AT89C51 单片机为核心，辅以较简单的元器件和电路设计，在顺利完成循迹功能的前提下，又充分考虑到了外观、成本等问题，因此小车的大部分电路由手工焊接完成。在设计中，我们没有在电路中增加冗余的功能，但是保留了各种硬件接口和软件子程序接口，方便以后的扩展和开发。

二( 系统硬件设计

2. 1 电机驱动模块设计

在制作智能小车时, 后左、右轮分别用两个转速和力矩基本完全相同的直流减速电机进行驱动, 车头前部装一个方向轮, 然后通过 I/O 口控制两个直流减速电机的转速和转向就可以实现小车的左转、右转和直行。

电机驱动采用一片集成电机驱动芯片L 298N。L298N是ST公司的产品, 内部包含 4通道逻辑驱动电路, 是一种二相和四相电机的专用驱动器, 即内含二个H 桥的高电压大电流双全桥式驱动器, 接收标准 TTL逻辑电平信号, 可驱动 46V、2A 以下的电机。

2. 2 寻迹模块设计

寻迹模块主要由光电反射式传感器组成。光敏电阻的阻值随周围环境光线的变化而变化, 当光线照射到白线上面时, 光线发射强烈; 光线照射到黑线上面时, 光线发射较弱。因此当光敏电阻在白线和黑线上方时, 阻值会发生明显的变化, 将阻值的变化值经过比较器就可以输出高低电平。但是这种方式受环境影响大, 工作不稳定。本文实际采用的是 RPR220 型反射式传感器制作的寻迹模块。

RPR220是一种一体化反射型光电探测器, 其发射器是一个砷化镓红外发光二极管, 而接收器是一个高灵敏度硅平面光电三极管。当发光二极管发出的光反射回来时, 三极管导通并输出低电平。

2. 3 避障模块设计

避障模块主要由红外反射式传感器组成。红外反射式传感器由 1 个红外发射管 (发射器 )和 1个光电二极管 (接收器 )构成, 红外发射管发出的红外光在遇到反光性较强的物体后被折回, 被光电二极管接收, 引起光电二极管光生电流的增大, 将此变化转为电压信号, 就可以被处理器接收并处理。

2. 4 遥控模块设计

本模块发射端采用高灵敏的 H L - 5000型万能电视遥控器, 接收端采用接收频率为 38kH z的万能接收头 1838, 该模块与单片机接口非常方便。另外, 对于经红外接收后的编码信号, 本系统设计时运用AT89C52单片微机的外部中断来接收, 信号的下降沿触发外部中断。为了识别一个完整的键信号, 必须对每一个编码脉冲的宽度进行测量, 以判别接收到的脉是 ! 0?还是 ! 1?, 利用单片机中的定时器 /计数器来测量脉冲宽度。定时器 /计数器的除分比是可以设定的, 从除 2到除 2048, 可测量的脉冲宽度可达 500m s。本文设定的除分比为 12, 即 12分频, 因为外部时钟约为 12MH z, 时钟周期为 1 s, 所以定时器 /计数器每计时一次为 1 s。

2. 5 报警模块设计

报警模块的核心芯片选择 110报警 IC, 可应用于汽车、摩托车、防盗器、个人防暴器、门磁报警器等场所。

三( 系统软件设计

本系统软件采用模块化结构, 由主程序)初始化子程序、中断子程序、延时子程序、按键发音子程序、按键扫描子程序构成。

3. 1 寻迹子程序设计

寻迹模块设计是通过把左右光电传感器的输出端分别接到单片机的 P 22 和 P23 管脚上, 然后通过单片机编程, 产生 PWM 控制信号, 通过 L 298控制电机的转速, 让小车达到前进、左转、右转及停止行驶的目的。

3. 2 避障子程序设计

避障模块设计是通过把左右红外反射式传感器模块的输出端分别接到单片机的 P20和 P21管脚上, 然后通过单片机编程, 产生 PWM 控制信号, 通过 L298控制电机的转速, 让小车达到前进、左转、右转及停止行驶的目的。

3. 3 遥控子程序设计

遥控模块设计是通过把红外接收头 1838的输出端接到单片机的 P32管脚上, 然后用万能遥控器对其进行遥控, 接着让单片机解码, 产生 PWM 控制信号,通过 L298控制电机的转速, 让小车达到前进、左转、右转及停止行驶的目的。

四(总结

采用单片机为核心, 利用光电传感器和红外反射式传感器作为探测系统, 设计了可以实现自动寻线行走、自动避障、报警以及遥控等功能的智能小车。该设计的显著优点是电路简单、可靠性强、成本低, 并且非常易于功能进一步完善和扩展。

Electric intelligent car based on SCM

Through research and to realize a photoelectric sensor for sensitive components, with AT89C51 as control core electric tracing of intelligent control carbonylation-the car，The system is also including dc motor, L9110 chips and LM324 comparator etc. The design USES AT89C51 as intelligent car core controller。

The system takes microcontroller as control core and realization of electric before Enter, back, turn left and right turn function. Through the Angle sensor [1] detection The seesaw Angle change, use incremental PI algorithm [2] to control the electric Car for balance, and using photoelectric sensor detection black line, make the electricity Actuation vehicle in the course of driving keep linear motion and don't skip from atrium。

1.Project Design

light by a sensor, the reality of the electric car is moving quickly degrees, bit, buy, transportation line shape when measured quantity of real condition, and will be measured quantity number according to preach sent to monolithic machine into line processing, but by single chip machine according to the measured by root different forms of several inspection according to real now to electric actuation vehicle wisdom can control system. This kind of square case can real now to electric actuation vehicle dynamic shape state into the shipment do real possession in system, control system spirit alive, can depend, pure degree is high, can full foot of each item of the stockings to beg. (1) straight epidemiological speed is tasseled straight epidemiological speed department with pulse width modulation experience.meanwhile gather speed is experience.meanwhile, its main electrical pulse width modulation by road system type variable change device, Jane says PWM variable change device. Adjustable speed by in the department of PWM experience.meanwhile open shut frequency rate is high, only on electricity barnado electricity sense of filter wave can be use to get to move very small straight pulse electric flow, electricity flow barnado electric capacity easily even tantras, department of low speed operation flat experience.meanwhile, adjustable speed stability van is surrounded relatively wide, can reach 1 000 left right. By on electrical flow wave shape than V - M system, be in phase with flat to all electrical flow dynamic machine, electric heat consumption and hair loss than a small. With the sample by in open shut frequency rate is high, and if a fast speed of electrical machine ring should match close, fasten tasseled phase can be to get very wide frequency band, because of the fast speed ring should be good, dynamic configuration sexual can perturbation resistance can force is powerful. According to the root, with more than ensemble close and this set of electrical machine control project by tolerance of the quantity and electrical machine speed straight flow of hair, the exhibitor to adopt the project with a single extremely H type can be changed into change device inverse PWM line speed.

1.1 photoelectric detection module design

The intelligent car was stuck on the black line running on white paper "road", so

this module design need to detect shop on the black rubber belt drive area, including Run straight along the arc district and driving district two area. Because of the black and white paper to light reflection coefficient is different, can according to receive reflected light.

The strength of the judge "road" - the black line. This paper USES is simple and practical detection methods, namely the infrared detection method.

Infrared detection method, i.e. use infrared ray in different colors of physical surface with different reflection properties characteristics. In the car driving process Continually to the ground to launch the infrared, when the infrared met white ground occurs when the reflected light, aimless and launch packed on the car of receiving tube receiving; if Fruit is met black line is absorbed, and then the infrared cars receiving tube receiving less than signal.

1. 2 signal comparative module design

This part design USES a LM324 comparator, of sensor signal voltage received compare and amplified, and will compare the results after Feed to the microcontroller, used to detect sensor sensitivity, diagram shown in figure 5 shows. When two sensors simultaneously detect light, straight forward. When the sensor can't detect light, in cut-off state, double LM324 operational amplifier output low level to microcontroller, by program processing, If left Not detected light, then left correct direction; If the right has not been detected light, then turn correct direction.

1. 3 motor control and driving module design

Because use is double drive cars, this part of the circuit must be able to output of two different voltage values, respectively to controlling trolley right and left two motor drive, the two of the wheel speed and direction of the same or different, thus to control its advance and turning. In system design process, use two L9110 chips to connect SCM and dc motor respectively. L9110 is for control and drive motor design two channels push-pull power amplifier application-specific integrated circuit device, discrete circuits in monolithic IC integrated such that the peripheral equipments in lower cost and the whole machine can carry on sexual high. The core slice two a TTL/CMOS and let electricity flat lose into, have good anti-jamming, Two output terminal can pick flooding dynamic electric machine straight to the shipment of positive reverse move and it has had a big electricity flow flooding dynamic can force, each call way can pass over 800mA continuous current, peak current capacity of 1. 5 ~ 0A; 2. At the same time it has lower output saturation pressure drop and the static electricity, The built-in clamp a diode can release the perceptual load of reverse current impulse, making it the drive relays, dc motors, stepping motor or switch power tube the use of safe and reliable.

Follow tracing car system to common AT89C51, complementary with relatively simple components and circuit design, the smooth completion of follow under the premise of tracing function, and fully considered appearance, costs, so most of the circuit car by manual welding is complete. In the design, we never in a circuit increase redundant functions, but retained various hardware interface and software

subroutines interface to facilitate the expansion and development after.

2. System hardware design

2. 1 motor driver module design

In making intelligent car, after left, right wheel respectively with two speed and Torque basic identical dc motor driven deceleration, bolt-on trunk-lid spoiler Department to install a direction wheel, then through the I/O mouth to control two dc slowing down Motor speed and steering can be achieved on the car to the left, turn right and straight Line.

Motor driver using a integrated electrical machine flooding dynamic core slice L 298N. L298N is ST the product of the company, the internal containing four channel logical drive circuit, it is a kind of two phase four phase motor drive, namely the special contains two H bridge of high voltage large current commander bridge type drive, acceptance criteria TTL logic level signals, be driven 46V, 2A below the motor.

2. 2 tracing module design

Tracing module mainly composed by photoelectric sensor reflex.

Photoconductive resistance of the resistance of the light with the surrounding environment changes, when the LTT white lines above, light emission strongly; The LTT black line above, light emission are relatively weak. So when photoconductive resistance in white line and black line above the elements will occur significantly changes, the resistance changes value after comparator can output high level. But this way environmental influences big, work is not stable. This article actual use is RPR220 type reflex sensors made tracing module.

RPR220 is an integration of reflective photoelectric detector, the transmitter is a gaas infrared light emitting diode and the receiver is a high sensitivity silicon photoelectric triode flat. When the light emitting diode reflected back, triode conduction and output low level.

2. 3 obstacle avoidance module design

Obstacle avoidance module mainly composed by infrared reflection sensor. Infrared reflection sensor by one infrared tubes (launchers) and 1 photoelectric diode (receiver) constitute, infrared tubes out to meet the infrared object reflective sex strong after be turned back, by photoelectric diode receiving, cause photoelectric diode current increases, light born this change into voltage signal, it could be processor receives and processing.

2. 4 remote control module design

This module will launch end USES high sensitive H L - 5000 type universal television remote control, the receiver using receive frequency for 38kH z's receiving head 1838, this module and the single chip computer interface is very convenient. In addition, for the red outside meet after harvest of plait code letter number, the department tasseled set when shipped with project of AT89C52 single chip microcomputer external interruption to receive, signal the falling edge of trigger

external interruption. In order to recognize a complete key signal, must for each coding pulse width were measured with discriminant receives the pulse is! 0 ? still! 1

?, the microcontroller timer/counter to measuring pulse width. Timer/counter except points than can be set, from except 2 to except 2048, measurable pulse width can reach 500m s. This paper set except points for 12, namely than 12 points frequency, because the external clock is about 12MH z, clock cycle for 1 s, so the timer/counter for 1 per timing once s.

2. 5 alarm module design

Alarm module core chip 110 IC, can choose application in automobile, motorcycle, alarms, personal riot device, door magnetic alarm device and etc.

3. System software design

This system software modular structure, the main program, initial anti-fuzzy procedures, interrupt subroutines, delay subroutines, buttons pronunciation subroutines, buttons scanning subroutines constitutes.

3. 1 tracing subroutines design

Tracing module is designed by the left right photoelectric sensor output terminal receiving monolithic machine respectively, P 22 and P23 tube feet, then through the microcontroller programming, produce PWM control signal, through L 298 control motor speed, let the car to move forward, left turn, turn right and stop driving purpose.

3. 2 avoid barrier of programming

Obstacle avoidance module is designed by the infrared reflection sensor module around the output terminal receiving MCU respectively P20 and P21 tube feet, then through the microcontroller programming, produce PWM control signal, through L298 control motor speed, let the car to move forward, left turn, turn right and stop driving purpose.

3. 3 remote subroutines design

Remote control module is designed by the infrared sensor 1838 an output terminal of the receiving MCU P32 tube feet, then use all-purpose remote control on the remote control, then let microcontroller decoding, produce PWM control signal, through L298 control motor speed, let the car to move forward, left turn, turn right and stop driving purpose.

4 Summary

Adopts singlechip, using photoelectric sensor and infrared reflection sensor was designed as a detection system, can realize automatic homing line to walk, automatic obstacle avoidance, alarm and remote control functions such as intelligent car. This design is the obvious advantages of simple circuit, reliability, low cost, and very easy to function of further perfecting and expansion

范文三：单片机外文翻译外文文献英文文献基于单片机的电动智能小车

原文出自:http://bulo.hujiang.com/u/5067956/diary/38722/

基于单片机的电动智能小车

一(方案设计

1.1 光电检测模块设计

1.2 信号比较模块设计

1.3 电机控制与驱动模块设计

由于采用的是双驱动的小车，这部分电路必须能够输出两个不同的电压值，分别去控制小车的左、右两个驱动电机，使小车的两个车轮的转速和方向相同或不同，从而来控制它的前进和转弯。在系统的设计过程中，用两个 L9110 芯片来分别连接单片机和直流电机。L9110 是为控制

和驱动电机设计的两通道推挽式功率放大专用集成电路器件，将分立电路集成在单片 IC 之中，使外围器件成本降低，整机可靠性提高。该芯片有两个 TTL / CMOS 兼容电平的输入，具有良好的抗干扰性; 两个输出端能直接驱动电机的正反向运动，它具有较大的电流驱动能力，每通道能通过800mA 的持续电流，峰值电流能力可达 1.5 , 2.0A; 同时它具有较低的输出饱和压降与静态电流; 内置的钳位二极管能释放感性负载的反向冲击电流，使它在驱动继电器、直流电机、步进电机或开关功率管的使用上安全可靠。

二( 系统硬件设计

2. 1 电机驱动模块设计

2. 2 寻迹模块设计

2. 3 避障模块设计

2. 4 遥控模块设计

以设定的, 从除 2到除 2048, 可测量的脉冲宽度可达 500m s。本文设定的除分比为 12, 即 12分频, 因为外部时钟约为 12MH z, 时钟周期为 1 s, 所以定时器 /计数器每计时一次为 1 s。

2. 5 报警模块设计

报警模块的核心芯片选择 110报警 IC, 可应用于汽车、摩托车、防盗器、个人防暴器、门磁报警器等场所。

三( 系统软件设计

本系统软件采用模块化结构, 由主程序)初始化子程序、中断子程序、延时子程序、按键发音子程序、按键扫描子程序构成。

3. 1 寻迹子程序设计

3. 2 避障子程序设计

3. 3 遥控子程序设计

四(总结

Electric intelligent car based on SCM

1.Project Design

1.1 photoelectric detection module design

The intelligent car was stuck on the black line running on white paper "road", so

The strength of the judge "road" - the black line. This paper USES is simple and practical detection methods, namely the infrared detection method.

1. 2 signal comparative module design

1. 3 motor control and driving module design

subroutines interface to facilitate the expansion and development after.

2. System hardware design

2. 1 motor driver module design

2. 2 tracing module design

Tracing module mainly composed by photoelectric sensor reflex.

2. 3 obstacle avoidance module design

2. 4 remote control module design

external interruption. In order to recognize a complete key signal, must for each coding pulse width were measured with discriminant receives the pulse is! 0 ? still! 1

2. 5 alarm module design

Alarm module core chip 110 IC, can choose application in automobile, motorcycle, alarms, personal riot device, door magnetic alarm device and etc.

3. System software design

3. 1 tracing subroutines design

3. 2 avoid barrier of programming

3. 3 remote subroutines design

4 Summary

范文四：基于单片机的称重软件设计外文文献

毕业设计（论文）

文文献译文及原

学生：

学号：

院（系）：

专业：

指导教师：

2010 年 6 月 8 日

外文

输入/输出访问

在这一篇文章中，我们将会研究三种基本的输入／输出访问方法：程控I/O、中断驱动I/O以及直接存储器访问（DMA）。区别这三个方法的关键问题是处理器以怎样的深度介入I/O操作。讨论的重点是中断驱动I/O，这是因为它的基础是中断处理概念，而这是一个超过输入输出操作之外的普遍性问题。学习中断处理也有助于了解异常事件处理这一普遍性概念，其重要性不但有关I/O，而且有关计算机与其他系统控制函数的接口。

I/O寄存器的寻址

输入/ 输出设备经过输入/ 输出端口与一个处理机通信。经过输入端口，处理器接受来自输入／输出装置的数据。经过输出端口，处理器送数据给输入／输出装置。每个输入／输出端口包含一个小的寄存器组, 如数据缓冲寄存器 (输入缓冲器和/或输出缓冲器)、状态寄存器和控制寄存器。处理器必须有某种方法寻址这些寄存器，同时与它们通信。寻址输入／输出寄存器有存储器映射输入／输出和直接输入／输出两种方法。

1 存储器映射的输入／输出

存储器映射的输入／输出将输入／输出寄存器和存储器一起映射到计算机系统的统一的住址空间。输入／输出寄存器共享主存储器的同一个地址空间, 但是被映射到一个特定的专为输入／输出预留的存储器区段。因此，输入／输出寄存器能在普通的存储器访问指令中得到寻址，好像它们就是主存储器位置的一部份。在计算机的指令系统中没有专门设计的输入／输出指令。任何访问这一地区中某个位置的指令便是一条输入/输出指令。任何的一条可以指定存储器地址的指令都可以执行输入／输出操作。摩托罗拉 MC68000 就是使用这种寻址方法的计算机系统的一个例子。

2 直接输入／输出

直接地向输入／输出寄存器寻址而不和主存储器共享地址空间的寻址方法叫做直接输入／输出或输入／输出映射输入／输出。换句话说，输入／输出寄存器不和主存储器映射到同一个地址空间。每个输入／输出寄存器有一个独立的地址空间。其结果是：访问主存储器空间的指令不能够作用于输入/输出。在计算机系统的指令系统中，必须为输入／输出操作设计专门的指令。在这些输入／输出指令中，必须用各自不同的标号来寻址不同的输入／输出交换通道。它们被称作端口号。输入／输出端口的输入／输出寄存器连接到系统输入／输出总线上，处理器经过它可以直接访问输入／输出寄存器向 / 从输入／输出装置发送 / 接收数据。使用端口号的方式和使用存储器地址的方式相同，但不同的是端口号不是来自主存储器的同一地址。Pentium 是使用直接输入／输出寻址法的计算机系统的例子。它有 64 GB 存储地址空间 (32 位住址)，同时，还有一个 64 KB 输入／输出地址空间 (16 位输入／输出住址/ 端口号)。

我们能依下列各项比较存储器映射输入／输出和直接输入／输出：:

存储器映射输入／输出使用普通的存储器访问指令访问输入／输出，因此它提供输入／输出编程的灵活性，并简化输入/输出软件。直接输入/输出不具备输入/输出编程的灵活性，因为只有一个小的特殊输入／输出指令被允许访问输入／输出寄存器。

有存储器映射输入／输出时，处理器使用相同的住址线访问所有的可寻址输入／输出寄存器和用相同的数据线向 / 从这些寄存器发送 / 接收数据。这样简化了输入／输出端口和处理器之间的连接，因而导致廉价的硬件设计和实现。对于直接输入／输出，输入／输出端口和处理器之间的连接可能成本比较高。这是因为需要专门的硬件实现分开的输入／输出住址线，或者当存储器地址线用于输入／输出的时候,需要一个特殊的标志来指出所要求的住址是为了输入／输出操作的。

尽管使用普通的存储器访问指令访问输入／输出寄存器有它的优点，但存储器映射输入／输出可能会使控制器的设计较复杂一些，这涉及与输入／输出相关的指令的实现。这是因为通常输入／输出总线周期比较等价的存储器总线周期要长一些，需要循环，而这意味着需要设计不同的时序控制逻辑。这能用来解释为什么存储器映射输入／输出有利于程序设计师, 但是不是电子学工程师。

直接输入／输出寻址有另一个高于存储器映射输入／输出的优点，即低级程序调试在用分开寻址系统中可能要更容易些, 因为断点和错误陷阱的设置比较通用。

在存储器映射输入／输出中，输入／输出寄存器和主存储器共享同一地址空间，因此，程序和数据可以使用的存储空间就减少了。对于直接输入／输出寻址，输入／输出不用和主存储器共享存储空间，可以维持一个单独的连续存储空间给程序员使用。

程控输入／输出

程控输入／输出需要全部数据操作处于处理机执行程序的完全控制之下。因为程序重复地巡查 (检查) 一个输入／输出装置的状态标志，所以有时它被称为巡查，而且它的输入/ 输出操作能与处理器同步。程序不断地巡查一个输入／输出装置的状态，以发现数据是否是已在输入缓冲中或输出装置有没有为接收从来自处理器的数据做好准备。如果状态显示

上面叙述的程控输入／输出操作模式是以程序的忙碌等待回路为特征的, 在它运行时处理器花费时间巡查一个输入／输出装置。因为处理器专注于一个单一的作业，这种程控输入／输出模式被称为专注式巡查或回旋式巡查。虽然专注式巡查十分低效, 但是有时它是必需的，甚至是不可避免的。在一个特别的情形中，如果一件紧急的事件需要没有延迟立即响应,则用一台专门的计算机做专注式巡查可能是最好的处理方法。一旦预期的事件发生, 处理器可以立刻反应。举例来说, 某些实时系统 (如

雷达回波处理系统) 需要对收入的数据极快的反应，甚至是一次中断反应都嫌太慢。在这样的环境之下，只有专注式巡查回路才足够应付。

程控输入／输出的另一个操作模式叫做间歇式巡查或定时巡查。在这一个模式中，处理器可在有规则的（预期的或事先规划的）时间间隔巡查设备。这种设备在许多嵌入式系统中可以看到，其中一台专用计算机用于过程控制、数据采集、环境监测、流量计数等。这些设备量测、收集或记录数据,通常是按照有规则的时间表进行周期性的巡查，其规划由应用对象的需要决定。这种间歇式巡查方法可以有助于节省回旋式巡查所浪费的时间，并且避免中断处理的复杂性。然而应该注意，间歇式巡查可能不适用某些特别的情形, 只有一个装置被巡查而正确的巡查又一定要借助一个由中断驱动的时钟才能得到。在这种情况使用定时巡查只能是简单的交替一次又一次中断需求。

中断驱动输入／输出

中断驱动输入/输出是一种能避免程控输入 / 输出特有的低效忙碌等待回路的方法。当输入 / 输出设备忙于它的输入输出作业时，处理机不是等待，而是可以运行其他的程序。当输入/输出设备完成它的作业而使其状态变为“已备好”时，它将向处理机发出一个中断请求，要求CPU的服务。作为响应，处理机挂起它正在做的任何工作，以便照顾该输入 / 输出设备的需要。

为了响应中断请求, 处理器将会首先为正在运行中的程序保存好程序计数器和状态计数器的内容，然后转移控制到对应的中断服务程序，以执行要求的输入/输出操作。当中断服务程序已经执行完毕时，如果没有更多的中断请求在等待,处理器将恢复状态寄存器和程序计数器的内容，恢复执行原先被中断的程序。处理器的硬件应该在每条指令执行结束时检查中断请求信号。如果有多个装置同时发行它们的中断请求,处理器必须利用某些方法选择哪一个首先服务, 然后再根据优先权的次序逐个的服务所有其他的中断请求。只有当所有的中断请求都已得到服务，CPU 才返回被中断的用户程序。这样，处理器能并发的服务于多个输入／输出装置，而且用较多的时间做有用的工作, 而不去运行一个忙碌等待回路为单个装置服务。因此,中断驱动输入 / 输出在处理慢速和中速输入 / 输出/设备方面是很有效的。此外，中断的观念可以被推广到处理任何由硬件或软件从内部或外部产生的事件。这一普遍性问题称为异常事件处理。

如果多个中断请求有不同的设备同时发出,处理器应该有某种方法识别中断来源而且按照某种策略（典型的是按优先权）处理它们的中断请求。现时只能有一个带最高优先权的请求可以得到服务, 所有其它的请求都放入一个候补等待的队伍之内。在中断服务程序执行服务完毕，处理器应该搜索等待的队列，找出所有正在等待中的旧的或新的中断请求, 并按照优先权逐个继续为它们服务，直到等待的队伍变空为止。只有当所有等待着的中断请求都已经得到服务，才会唤回被中断的用户程序。虽然这一个情形包含了多个中断请求, 但是它仍然是一个被单一化的情形。假定：所有的中断服务程序一旦被处理器一个接一个的启动，它们便必须完成而不再由中断或所谓抢占发生。满足这一假设的中断过程称为非抢占中断。在真实的环境中，中断驱动输入／输出的过程比这个简化过程更为复杂。每个正在处理机中运行的中断服务程序可以被新来的中断请求所抢占（中断），只需它的优先权比现有的优先权高。这一个环境将会引起主程序和所有被要求的中断服务程序之间有一个复杂的相互关系。允

许中断服务程序被较高优先权的中断服务程序所强占的中断过程叫做抢占中断。

直接存储器访问

虽然中断驱动输入／输出比被程控输入／输出有效率, 但是它仍然受限于较高的与中断处理有关的开销。这一开销包括解决多个中断请求之中的冲突、保存和恢复程序现场、用于中断辨认的巡查、中断服务程序的来回转移等。使用中断是一个浪费的活动，它费时好几个微秒才能完成。

直接存储器访问(DMA) 是一个向 / 从主存储器直接输入输出字块的方法，速度是每一存储周期一个数据项，而无需处理机的连续参与。整个过程由DMA控制器的硬件实现, 它代替处理器而直接与主存储器通信。结果，计算机系统的框图由以处理机为中心变为以存储器为中心。因此，从输入／输出处理的观点来看，处理器不再是计算机的中心, 而只是一个伙伴，输入／输出子系统和它竞争存储器总线周期，向 / 从主存储器输入输出数据。然而，DMA控制器是设计成

以字块交换数据，因此，它能很好的和大容量高速度面向字块的输入／输出装置, 例如高速磁盘通信网络，一起工作。.

DMA控制器能在两个不同的模式下工作。正常情况下，它与处理器并发的工作, 竞争零星的存储器总线周期，以输入输出一个字块的连续的字。如果输入／输出速度不是很高,处理器的存储器访问和DMA 控制器访问可以交叉进行。时间可以在周期到周期的基础上增加。在任何一个时间段，处理器或DMA控制器都不能连续的使用所有的存储器总线周期。 DMA控制器的这一操作模式叫做周期窃取。如此命名是因为输入／输出子系统实质上是从处理器“窃取”存储器总线周期。这一个模式把直接内存存取的存储器访问整合在CPU活动中，避免严重的打扰主要的处理任务。另一方面，对于更高的输入／输出传输率，直接内存存取操作需要总线时间能安排在成块的周期内，这称为爆发。在存储周期的爆发中，处理器完全地被排斥在存储器访问之外。直接内存存取控制器被给与主存储器的排他性访问，连续的输入输出数据字块，其速度可以和存储器速度相比较。直接内存存取控制器的这一操作模式被称为字块模式或爆发模式。为这一操作模式设计的直接内存存取控制器通常结合一个数据存储缓冲器，其容量至少与一个字块相匹配。当DMA控制器利用存储器总线时，它可以直接在它的数据存储缓冲器和主存储器之间交换一个字块。

下列各寄存器对于DMA 传输一个字块是必要的：

数据缓冲寄存器 (DBR) ——它可以实现为两个寄存器, 一个用于输入，另一个用于输出, 或者甚至于一个寄存器组，组成一个数据存储缓冲器。

DMA 地址寄存器 (DAR) —— 用来存放存储器缓冲区（用来读写字块）的起始地址。

字计数器 (WC) ——由它的内容指定字块中余下尚待传输的字数，每一个字传输以后字数自动减值。

控制 / 状态寄存器 (CSR)——处理器用来发送控制信息给直接内存存取控制器并且收集直接内存存取控制器和它所连输入／输出装置的状态和出错信号。

利用这些寄存器,直接内存存取控制器能知道源字块和目的字块, 以及将要传输的数据量。一旦直接内存存取控制器获得了存储器总线，便可以利用这些寄存器中包含的信息，自主地执行字块传输操

作，而无需处理器的连续介入。

在上列寄存器之外，直接内存存取控制器还应该包含总线请求设备的控制逻

辑,它利用直接内存存取请求 (DMAR) 和直接内存存取回答 (DMAA)信号执行总线仲裁。总线仲裁是一个分解冲突的过程，用来解决多个并发请求之间产生的冲突，这些请求都想要操作直接内存存取控制器以获取存储器总线。总线主方的确定通常是基于不同的DMA 装置具有的优先权。在不同的直接内存存取装置之中，由装置接收直接内存存取服务的紧迫程度，也就是它们的速度需求，来安排优先权次序。为直接内存存取装置进行总线仲裁有两个方法——集中式和分布式，它们和利用中断请求 (INTR) 和中断应答 (INTA)信号以辨认中断源的方法是相似的。

虽然直接内存存取执行字块传输没有处理机参加, 但是直接内存存取控制器的总体操作仍然是由CPU 通过中断来决定的。它有两个目的：(1)在直接内存存取控制器启动数据传输之前，所有的寄存器必须由处理器设定初值；(2) 当直接内存存取完成一个字块传输操作时,它应该发出一个中断告知处理器操作完成，以允许处理器在存储器缓冲区进行数据的后处理或者处理可能的错误情况。因此，直接内存存取控制器时常发出中断请求 (INTR) 和接受中断的回答 (INTA) 信号。

DMA 减轻处理器在输入／输出功能上的负担,但叁数传输初始化和数据的后处理除外。当服务高速的输入／输出装置的时候，这是非常有效的。然而，直接内存存取的作用并不限于输入输出区域。在现代的计算机系统中，直接内存存取已经发展为一个通用的技术，它在输入／输出子系统处理和CPU 处理之间进行主存储器带宽的分时。在输入／输出子系统中，高速的输入／输出装置，像磁盘，CD-ROM，DVD，图像，视频设备和高速网络都要经过直接内存存取分享主主存储器的带宽。在中央处理和主存储器范围，运行中的程序、操作系统以及动态随机存取储存器的再生都要分享主存储器带宽。直接内存存取是一个适当的方法来实现这种分时。比较快速的16位Ultra DMA 现在已经代替旧式的8位设备。现在可用的商售直接内存存取控制器芯片及已经提供多个通道,允许并发的数据传输。例如，一个通道可以保留给动态随机存取储存器再生，另外的一个通道能执行存储器到存储器的字块移动等。为了进一步让处理机免于处理慢速作业，已经开发了强功能的通道处理机，它有自主的能力，包括设备巡查、通道程序执行、中断激活以及数据和指令的直接内存存取。它们已经作为成长中的一类半独立的分处理器与主处理器通信。它们被指定专门的工作，例如浮点运算、图像处理、网络通信、大规模数据库管理等。由于主存储器带宽分时而日益增大的总线竞争问题可以通过更有效的利用高速缓存予以淡化。例如，在 Pentium 处理器中，只要缓存本地保存的指令能满足要求，L1 缓存便允许CPU 流水线继续读取和执行指令。

Input/Output Accessing

In this article, we will look at the three basic methods of I/O accessing － programmed I/O, interrupt-driven I/O, and direct memory access (DMA). The key issue that distinguishes these three methods is how deeply the processor is involved in I/O operations. The discussion emphasizes interrupt-driven I/O, because it is based on the concept of interrupt handling, which is a general problem that goes beyond Input/Output operations. The study of interrupt handling also aids in understanding the general concept of exception processing, which is an important issue not only for I/O, but also for interfacing a computer with other system control functions.

Addressing I/O Registers

Input/Output devices communicate with a processor through Input/Output ports. Through the input ports, s processor receives data from the I/O devices. Through the output ports, a processor sends data to the I/O devices. Each I/O port consists of a small set of registers, such as data buffer registers (the input buffer and/or the output buffer), the status register, and the control register. The processor must have some means to address these registers while communicating with them. There are two common methods of addressing I/O register － memory-mapped I/O and direct I/O.

1. Memory-Mapped I/O

Memory-mapped I/O maps the I/O registers and main memory into a unified address space in the computer system. I/O registers share the same address space with main memory, but are mapped to a specific section that is reserved just for I/O. Thus, the I/O register can be addressed in ordinary memory reference instructions as if they are part of the main memory locations. There are no specially designed I/O instructions in the instruction set of the system. Any instruction that references a location in this area is an I/O instruction. Any instruction that can specify a memory address is capable of performing I/O operations. The Motorola MC68000 is an example of a computer system that uses this addressing method.

2. Direct I/O

The method of addressing I/O registers directly without sharing the address space with the main memory is called direct I/O or I/O-mapped I/O. In other words, I/O registers are not mapped to the same address space with the main memory. Each I/O register has an independent address space. As a result, instructions that reference the main memory space cannot be used for Input/Output. In the instruction set of the computer system, special I/O instructions must be designed for I/O operations. In these I/O instructions, distinct I.D. numbers must be used to address different I/O communication channels (i.e., I/O ports). They are called port numbers. The I/O registers of an I/O port are connected to the system I/O bus, through which the processor

can reference the I/O registers directly to send/receive data to/from an I/O device. An I/O port number is not from the same address space as main memory. The Pentium is an example of a computer system that uses the direct I/O addressing method. It has a 64 GB memory address space (32 address bits) and, at the same time, a 64 KB I/O address space (16 bits I/O address/port number).

We can compare memory-mapped I/O and the direct I/O and the direct I/O as follows:

Memory-mapped I/O uses ordinary memory reference instructions to access I/O, so it provides flexibility for I/O programming and simplifies I/O software. Direct I/O does not provide any flexibility in I/O programming, since only a small set of special I/O instructions are allowed to reference I/O registers.

for memory-mapped I/O, the processor uses the same address lines to access all the addressable I/O registers and the same data lines to send/receive data to/form these registers. This simplifies the connection between I/O port and the processor, and thus leads to a low-cost hardware design and implementation. For direct I/O, the connection between I/O ports and the processor may be more expensive. This is because either

(1) special hardware is needed to implement separate I/O address lines or (2) when memory address lines are used for I/O; a special flag is needed, indicating that the requested address is for an I/O operation.

In spite of the advantage of using ordinary memory reference instructions to access I/O registers, memory-mapped I/O may complicate the control unit design in regards to the implementation of I/O-related instructions. This is because usually the I/O bus cycles need to be longer than the equivalent memory bus cycles, and this means that the design of different timing control logic is required. This can be used to explain why memory-mapped I/O benefits programmers, but not electronics engineers.

Direct I/O addressing has another advantage over memory-mapped I/O in that low-level debugging on a differentiated addressing system may be easier, because break-points or error traps can be imposed more generally.

with memory-mapped I/O, I/O registers share the same address space with main memory; hence, the memory space available for programs and data is reduced. For direct I/O addressing, I/O does not share memory space with main memory, and a single contiguous memory space can be maintained and used by programmers.

Programmed I/O

Programmed I/O requires that all data transfer operations be put under the complete control of the processor when executing programs. It is sometimes called polling, because the program repeatedly polls (checks) the status flag of an I/O device, so that its input/output operation can be synchronized with the processor. A general flowchart of such a program is shown in Figure 1. The program continuously polls the status of an I/O device to find out whether (1) data is available in the input buffer or (2) the output device is ready for receiving data from the processor. If the status shows “available” the program will execute a data transfer instruction to complete the I/O operation; otherwise, the busy status of the I/O device will force the

program to circulate in a busy-waiting loop until the status becomes available. Such a busy-waiting loop, which continuously checks the status of data availability (for input) or device availability (for out-put), forms the typical program structure of programmed I/O. It is this time-consuming busy-waiting loop that wastes processor time and makes programmed I/O very inefficient. The processor must be involved continuously in the entire I/O process. During this time interval, the processor cannot perform any useful computation, but only serve a single I/O device. For certain slow I/O devices, this busy-waiting loop interval may be long enough that the processor could execute millions of instructions before the I/O event occurs, e.g., a key stroke on a keyboard.

The operational mode lf programmed I/O stated above is characterized by the busy waiting loop of the program, during which the processor spends time polling an I/O device. Because of the dedication of the processor to a single task, this mode of programmed I/O is called dedicated polling or spin polling. Although dedicated polling is highly inefficient, sometimes it is necessary and even unavoidable. In a particular case, if an urgent event needs an immediate response without delay, then dedicated polling by a dedicated processor may be the best way to handle it. Once the expected event happens, the processor can tract to it immediately. For example, certain real time systems (e.g., radar echo processing systems) require a reaction to incoming data that is so quick that even an interrupt response is too slow. Under such a circumstance, only a fast dedicated polling loop may suffice.

Another mode of operation of programmed I/O is called intermittent polling or timed polling. In this mode, the processor may poll the device at a regular timed interval, which can be expected or prescheduled. Such a device can be found in many embedded systems where a special-purpose computer is used for process control, data acquisition, environmental monitoring, traffic counting, etc. these devices, which measure, collect, or record data, are usually polled periodically in a regular schedule determined by the needs of the application. Such a method of intermittent polling can help save time lost in spin polling and avoid the complexity of interrupt processing. However, it should be noted that intermittent polling may not be applicable in some special cases, in which there is only one device to be polled and the correct polling rate must be achieved with the assistance of an interrupt-driven clock. Using timed polling in this case would result in simply swapping one interrupt-driven clock. Using time polling in this case would result in simply swapping one interrupt requirement for another.

Interrupt-Driven I/O

Interrupt-driven I/O is a means to avoid the inefficient busy-waiting loops, which characterize programmed I/O. Instead of waiting while the I/O device is busy doing its job of input/output, the processor can run other programs. When the I/O device completes its job and its status becomes “available”, it will issue an interrupt request to the processor, asking for CPU service. In response, the processor suspends whatever it is currently doing, in order to attend to the needs of that I/O device.

In respond to an interrupt request, the processor will first save the contents of both the program counter and the status register for the running program, and then transfer the control to the corresponding interrupt service routine to perform the required data input/output operation. When the interrupt service routine has completed its execution and if no more interrupt requests are pending, the processor will resume the execution of the previously interrupted program and restore the contents of the statuses and program counter. The processor hardware should check the interrupt request signal upon completion of execution of every instruction. If multiple devices issue their interrupt requests at the same time, the processor must use some method to choose which one to service first, and then service all the other interrupt requests one by one by order of priority. Only after all the interrupt requests have been serviced will the CPU return to the interrupted user program. In this way, the processor can serve many I/O devices concurrently and spend more time doing useful jobs, rather than running a busy-waiting loop to serve a single device. Therefore, interrupt I/O is very effective in handling slow and medium-speed I/O devices. Furthermore, the concept of an interrupt can be generalized to handle any event caused by hardware or software, internally or externally. This general problem is referred to as exception processing.

If multiple interrupt requests are issued by different devices at the same time, the processor should have some means to identify the interrupt sources and handle their interrupt requests by some policy, typically by priority. Only one request with the highest priority can be serviced at the current time, while all others are put into a waiting queue. Upon the completion of the service performed by an interrupt service routine, the processor should search the waiting queue for all the pending interrupt requests, old or new, and continue to service them one by one according to their priorities, until the queue becomes empty. Only when all the pending interrupt requests have been serviced can the interrupted user program be resumed. Although this case contains multiple interrupt requests, it is still a simplified case. The assumption is that all the interrupt service routines must be completed without further interruption 9 (or so-called preemption) once they have been started one after another by the processor. An interrupt process satisfying this assumption is called a non-preemptive interrupt. In real-life circumstances, the process of interrupt-driven I/O can be more complicated than this simplified case. Each interrupted service routine running in the processor can be preempted (interrupted) by a newly arrived interrupt request, which has a higher priority than the current one. This circumstance will cause the main program and all the requested interrupt service routines to have a complicated interrelationship. An interrupt process that allows an interrupt service routine to be preempted by a higher-priority interrupt service routine is called a preemptive interrupt.

Direct Memory Access

Although interrupt I/O is more efficient than the programmed I/O, it still suffers from a relatively high overhead with respect to handling the interrupt. This overhead includes resolving the conflict among multiple interrupt requests, saving and restoring the program contexts, pooling for interrupt identification, branching

to/from the interrupt service routine, etc. Using an interrupt is a wasteful activity that can take several microseconds to complete.

Direct memory access (DMA) is a method that can input/output a block of data directly to/form main memory with a speed of one data item per memory cycle, without continuous involvement of the processor. The entire process is implemented by the hardware of a DMA controller, which takes the place of the processor and communicates directly with main memory. As a result, the block diagram of the computer system changes form processor-centered to memory-centered. Hence, from the viewpoint of I/O processing, the processor is no longer the center of a computer, but rather a partner with which the I/O subsystem competes for memory bus cycles to input/output data item to/from main memory. However, a DMA controller is designed to exchange data in blocks, so it works well with the large-volume high-speed block-oriented I/O devices, such as high-speed disks and communication networks.

The DMA controller can work in two different modes. Normally, it works concurrently with the processor, competing for individual memory bus cycles to input/output successive words of a data block. If the I/O speed is not very high, the memory accesses by the processor and the DMA controller can be interwoven. Time is accrued on a cycle-by-cycle basis. Neither the processor nor the DMA controller can continuously use all the memory bus cycles during any time interval. This operational mode of the DMA controller is called cycle stealing, so named because the I/O subsystem is essentially “stealing” memory bus cycles from the processor. This mode integrates the DMA memory accesses into CPU activity and avoids serious disruption of the main processing. Alternatively, for even higher I/O transfer speed, DMA operations require bus time, which can be allocated in block of cycles known as bursts. During a burst of memory cycles, the processor is totally excluded from accessing memory. The DMA controller is given exclusive access to main memory and continuously inputs/outputs blocks of data at a speed comparable to the memory speed. This operational mode of the DMA controller is called the block or burst mode. A DMA controller designed for this mode of operation usually incorporates a data storage buffer with a capacity matching the size of at least one data block. When the DMA controller utilizes the memory bus, it can transfer a data block directly between its data storage buffer and main memory.

The following registers are necessary for the DMA to transfer a block of data:

Data buffer register (DBR) － it can be implemented as two registers, one for input and the other for output, or even a set of registers comprising a data storage buffer.

DMA address register (DAR) － used to store the starting address of the memory buffer area where the block of data is to be read or written.

Word counter (WC) － the contents specify the number of words in the block of data remaining to be transferred and it is automatically decremented after each word is transferred.

Control/status register (CSR) － used by the processor to send control information to the DMA controller and to collect the statuses and error information of the DMA controller and the I/O device.

Using these registers, the DMA controller knows the addresses of the source and destination data blocks, as well as the quantity of data to be transferred. Once the DMA controller acquires the memory bus, the block transfer operation can be performed autonomously using the information contained in these registers, without the continuous involvement of the processor.

Besides the above-listed registers, the DMA controller should contain the control logic of a bus request facility, which performs bus arbitration using the signals of DMA request (DMAR) and DMA acknowledge (DMAA). Bus arbitration is the process of resolving the contention among multiple concurrently operating DMA controllers for acquisition of the memory bus. The selection of the bus master is usually based on the priorities of various DMD devices. Among different DMA devices, the priority order are arranged by the degree urgency of the devices receiving the DMA service, i.e., according to their speed requirements. There are two approaches to bus arbitration for DMA devices － centralized and distributed － which are similar to the approaches used to identify interrupt sources using signals for interrupt request (INTR) and interrupt acknowledge (INTA).

Although the transfer of the data block is performed by the DMA without involvement of the processor, the overall operation of the DMA controller is still determined by the CPU via interrupts. It serves two purposes as follows: (1) Before the DMA controller starts the data transfer, all the registers must be initialized by the processor. (2) When the DMA finishes a block transfer operation, it should inform the processor of completion by issuing an interrupt, which allows the processor to post-process the data in the memory buffer area or handle possible error conditions. Therefore, the DMA controller often issued interrupt request (INTR) and receives interrupt acknowledge (INTA) signals.

DNA relieves the processor form the burden of I/O function, except for the initialization of the transfer of parameters and the post-processing of data. It is very efficient when serving high-speed I/O devices. However, the role of DMA is not limited to the area of input/output. In contemporary computer systems, DMA has been developed into a general technique of time-sharing the main memory bandwidth between I/O subsystem processing and CPU processing. In the I/O subsystem, high-speed I/O devices, such as disks, CD-ROMs, DVDs, graphics, video equipment, and high-speed networks, want to share main memory bandwidth through the DMA. In the area of central processing and the main memory system, (1) running programs, (2) the operating system, and (3) dynamic RAM refreshing are all sharing the main memory bandwidth, DMA is the appropriate way to implement this time-sharing. Faster 16-bit Ultra DMA has now replaced the outdated 8-bit facilities. Commercially available DMA controller chips now offer multiple channels, allowing concurrent data transfer. For example, one channel can be reserved for DRAM refreshing; another channel can perform memory-to memory block moves, etc. To further free the processor from handling slow tasks, powerful channel processors have been developed with autonomous capabilities, including device polling, channel program execution, interrupt activation and DMA for data and instructions. They have become a growing class of semi-independent co-processors communicating with the main processor. They can be assigned

dedicated tasks, such as floating-point calculations, graphic processing, network communication, large database management, etc. The growing bus contention problem, due to time-sharing main memory bandwidth, can be alleviated by more effectively using cache memory. For example, in the Pentium processor, L1 cache allows the CPU pipeline to continue fetching and executing, as long as the demand can be satisfied with instructions held locally in the cache.

范文五：基于单片机控制的自动给水系统外文文献

燕京理工学院 YANCHING INSTITUTE OF TECHNOLOGY

外文文献原稿和译文

学院:机电工程学院专业:机械工程

学号:130310208

姓名:张磊

指导教师:王续明

2017 年 3 月

外文文献原稿和译文

原稿

The water supply system is the national production and life indispensable important one annulus. The traditional method of water supply area, water pollution, infrastructure investment, but the main drawback is that water can not be kept constant, causing part of the equipment can not work normally. Variable frequency speed control technology is a new mature AC motor stepless speed regulating technology, its unique excellent control performance is widely applied to the speed control field, especially in water supply industry. Due to the safety in production and the water quality of special needs, for constant pressure water supply with the stringent requirements, so the frequency control technology has been more in-depth application. Constant pressure water supply ways to advanced technology, constant pressure, convenient operation, reliable operation, energy saving, high degree of automation, in pump station water supply can perform the following functions:

(1) to maintain constant pressure;

(2) the control system can be manual or automatic operation;

(3) a plurality of pump automatic switch operation;

(4) system of sleep and wake, when people stop when water, the system is in a sleep state, until the water demand automatically wake;

(5) adjusts the PID parameters on line;

(6) pump unit and circuit protection detection alarm, signal display.

The actual pressure of the pipe network feedback and a given pressure were compared, when the pressure of a pipe network is low, increase the output of frequency converter, pump speed faster, water supply quantity increases, forcing the pipe network pressure rise. Vice pump speed slow down, reduce the water supply pipe network pressure drop,, to keep the constant pressure water supply.

System hardware structure

System uses a pressure sensor, PLC and inverter as a central control device, to

achieve a desired function. Source: network transmission and distribution equipment installation in pipe line pressure sensor, for detecting the water pressure of the pipe network, converting pressure is 4 ~ 20 mA current or voltage signal is 0 ~ 10V , supplied to the inverter.

Converter pump motor control device, in accordance with the constant water pressure needs to be 0 ~ 50 Hz frequency signal supply pump motor, adjust its speed SAJ converter is powerful, i.e. pre-programmed set parameter set, will use the required in the process of setting the number of parameters is reduced to a minimum, default value according to the application parameter of the macro choice and different. The system adopts the PID control application macro, closed loop control. Inverter based on a constant pressure corresponding to the voltage setting value and from the pressure sensor to obtain the feedback current signal, the use of PID control macro automatically adjust, change the frequency output value to adjust the control the speed of the pump motor, to ensure that the pipe network pressure constant requirements. The application of inverter in the constant pressure water supply

1.The characteristic and analysis of variable frequency speed regulation

The water users in general is dynamic, so the water supply is insufficient or excess water supply situation has occurred. The water supply and the imbalance between the concentrated reflection in water supply pressure, namely water and watersupply is less, the low pressure; less water consumption and water supply, the pressure. Keep the water pressure constant, can make the water supply and water balance between water supply and water for a long time, that is, less water when the water is less, so as to improve the quality of water supply.

Constant pressure water supply system for the user is very important. In production and living water, if water supply due to insufficient pressure or short of water, may affect the quality of life, serious when can influence the survival safety, such as when a fire occurs, if the water pressure is insufficient or water supply, can quickly fire, may cause significant economic losses and casualties. Therefore, water area by means of Arts is the constant pressure water supply system, can produce great economic benefit and social benefit.

With the development of electric power technology, frequency conversion technology perfected, with variable frequency speed control as the core of the intelligent water control system replaced the previous high level water tank and a pressure tank and water supply equipment, stable starting, the starting current can be limited within specified current, thereby avoiding the starting time of the impact of power grid; because the average rotational speed of pump is reduced, which can extend the pumps and valves and other things of life; to eliminate the start and stop of the water hammer effect. The stable and safe performance, simple and convenient operation, and complete and thoughtful function, will make the water supply and water conservation, energy saving, labor saving, ultimately achieve efficient operation.

2.The application of variable frequency control constant pressure water supply mode

Usually in the same way in the water supply system, setting multiple common pump, water supply when the quantity of multi pump full open, water supply on one or two hours. In the variable frequency speed control for constant pressure water supply, in two ways, one is all pumps with a frequency converter; and each water pump with a frequency converter. After a method based on pressure feedback signal, operated by PID automatically adjusts the output frequency of the inverter, change the speed of the motor, eventually reaching the purpose of network voltage, a closed loop, is relatively simple, but the cost is high. The previous method of low cost, less than kind of poor performance, but the control program is complex, is the future direction of development, such as the Shanghai arts and science and technology of constant pressure water supply control system can realize a inverter control any number of motor function. The principle mentioned below are multiple motor inverter drive system.

3.The PID control principle

According to the feedback principle: to maintain a physical quantity unchanged or essentially unchanged, it should bring the physical quantity and the constant comparison, to form a closed loop system. We want to keep the pressure constant, so we must introduce the hydraulic feedback value with a given value, thereby forming

a closed loop system. But the control system is characterized by nonlinear, inertial system, now the control method combined with PID in the large pressure fluctuation, using fuzzy control, in order to accelerate the response speed in the pressure range; using PID to maintain static accuracy. This through the PLC and intelligent instrument can show the algorithm, while the PLC programming to show when the pump frequency and inverter switching between. Practice has proved that, using this method is feasible, and the cost is not high.

4.Frequency control

Using frequency control to realize constant pressure water supply, with adjustable valve to realize constant pressure water supply, energy-saving effect is very significant (according to the specific circumstances calculated ). The utility model has the advantages of:

(1)Starting balance, the starting current can be limited within specified current, thereby avoiding the starting time of the impact of power grid;

(2)Because the average rotational speed of pump is reduced, thereby prolonging the service life of pump and valve etc.

(3)Can eliminate the start and stop of the water hammer effect;

Generally speaking, when performed by a frequency converter to control a motor, just make the inverter motor capacity and the actual capacity of the motor can be. When one inverter control two motors, principle of inverter motor capacity should be equal to the capacity of the two motors. But if the peak load of water more than two pumps at full supply a lot of difference, Shanghai arts and science and technology engineers suggested, may be considered appropriate to reduce the capacity of the frequency converter, but attention should be paid to leave enough capacity.

Although the pump at low speed, small working current of the motor. However, when the user with the water volume changes frequently, the motor will be in frequent ascending, descending and ascending, descending speed state, the current speed slightly over the motor rated current, cause the motor overheat. Therefore, the motor thermal protection is required. For this due to frequent ascending, descending speed and accumulated temperature rise, frequency converter in electronic thermal protection function is difficult to play a protective role, so should be used in thermal

relay for motor thermal protection.

The main function of preset, the highest frequency should be rated motor frequency converter the highest working frequency. Ascending, descending speed time in using PID regulator case, ascending, descending velocity time should be set to be short, so as not to affect the PID adjuster determines the dynamic response process. Such as the frequency converter with PID regulation function, as long as the preset set PID function effectively, the setting of the acceleration and deceleration time will automatically lapse.

译文

供水系统是国民生产生活中不可缺少的重要一环。传统供水方式占地面积大,水质易污染,基建投资多,而最主要的缺点是水压不能保持恒定,导致部分设备不能正常工作。变频调速技术是一种新型成熟的交流电机无极调速技术, 它以其独特优良的控制性能被广泛应用于速度控制领域, 特别是供水行业中。由于安全生产和供水质量的特殊需要, 对恒压供水压力有着严格的要求, 因而变频调速技术得到了更加深入的应用。恒压供水方式技术先进、水压恒定、操作方便、运行可靠、节约电能、自动化程度高,在泵站供水中可完成以下功能:

(1)维持水压恒定;

(2)控制系统可手动 /自动运行;

(3)多台泵自动切换运行;

(4)系统睡眠与唤醒,当外界停止用水时,系统处于睡眠状态,直至有用水需求时自动唤醒;

(5)在线调整 PID 参数;

(6)泵组及线路保护检测报警,信号显示等。

将管网的实际压力经反馈后与给定压力进行比较, 当管网压力不足时, 变频器增大输出频率,水泵转速加快,供水量增加,迫使管网压力上升。反之水泵转速减慢,供水量减小,管网压力下降,保持恒压供水。

工作原理

在供水系统中引进变频器结合小型 PLC 技术, 不仅改变传统用阀门控制水量多少, 而且在节能、恒压控制等方面均有非常好的效果, 本文介绍了变频器 --PLC 调控技术在水泵控制中的应用。控制系统用一台变频器可以带三台水泵, 每台水泵既可以工作在常规工频泵模式, 也可以工作在变频泵模式。每台泵只能处于变频或工频其中一种工作模式,通过两个继电器互锁保证它的安全与可靠。生活用水中的压力变送器将水的压力信号传输到调节器, 根据与调节器的设定值和报警上下限比较, 送信号给 PLC 与变频器, 系统的起停泵分别由调节器的压力下限信号和变频器的频率下限信号决定, 假如压力低, 调节器给 PLC 一个压力下限信号, PLC 启动变频器,并使一号泵处于变频工作状态, 输出的频率逐渐增大,经过一段时间的调节,如压力还低,这时, PLC 让一号泵处于工频状态

工作, 使二号泵处于变频工作状态泵, 如压力还低, 则让二号泵处于工频状态工作,使三号泵处于变频工作状态,如此类推。当压力达到调节器上限报警值时, 调节器输出降低, 变频器频率降低, 低到频率下限设定值, 这时变频器给出一个频率下限信号给 PLC , PLC 根据先启先停的原则控制泵的运行顺序,例如, PLC 收到频率下限信号时, 系统中泵的状态是一号工频,二号工频,三号变频,这时一号泵最先启动,所以先停,接着如压力还高,则停二号泵。系统采用了每次都进行低速启动,高速运行以提高运行效率。

系统硬件构成

系统采用压力传感器、 PLC 和变频器作为中心控制装置, 实现所需功能。来源 :输配电设备网安装在管网干线上的压力传感器,用于检测管网的水压,将压力转化为 4~20 mA的电流或者是 0~10V的电压信号,提供给变频器。变频器是水泵电机的控制设备,能按照水压恒定需要将 0~50 Hz的频率信号供给水泵电机, 调整其转速 SAJ 变频器功能强大, 即预先编置好的参数集, 将使用过程中所需设定的参数数量减小到最小, 参数的缺省值依应用宏的选择而不同。系统采用 PID 控制的应用宏, 进行闭环控制。变频器根据恒压时对应的电压设定值与从压力传感器获得的反馈电流信号, 利用 PID 控制宏自动调节, 改变频率输出值来调节所控制的水泵电机转速,以保证管网压力恒定要求。

变频器在恒压供水中的应用

一、变频调速的特点及分析

用户用水量一般是动态的, 因此供水不足或供水过剩的情况时有发生。而用水和供水之间的不平衡集中反映在供水的压力上, 即用水多而供水少, 则压力低; 用水少而供水多, 则压力大。保持供水压力的恒定, 可使供水和用水之间保持平衡,即用水多时供水也多,用水少时供水也少,从而提高了供水的质量。恒压供水系统对于用户是非常重要的。在生产生活供水时, 若自来水供水因故压力不足或短时断水,可能影响生活质量,严重时会影响生存安全,如发生火灾时, 若供水压力不足或或无水供应, 不能迅速灭火, 可能引起重大经济损失和人员伤亡。所以, 用水区域采用正艺恒压供水系统, 能产生较大的经济效益和社会效益。随着电力技术的发展, 变频调速技术的日臻完善, 以变频调速为核心的智能供水控制系统取代了以往高位水箱和压力罐等供水设备, 起动平稳, 起动电流可限制在额定电流以内,从而避免了起动时对电网的冲击;由于泵的平均转速降低了, 从而可延长泵和阀门等东西的使用寿命; 可以消除起动和停机时的水锤效应。其

稳定安全的运行性能、简单方便的操作方式、以及齐全周到的功能, 将使供水实现节水、节电、节省人力,最终达到高效率的运行目的。

二、恒压供水的变频应用方式

通常在同一路供水系统中, 设置多台常用泵, 供水量大时多台泵全开, 供水量小时开一台或两台。在采用变频调速进行恒压供水时, 就用两种方式, 其一是所有水泵配用一台变频器; 其二是每台水泵配用一台变频器。后种方法根据压力反馈信号, 通过 PID 运算自动调整变频器输出频率, 改变电动机转速, 最终达到管网恒压的目的,就一个闭环回路,较简单,但成本高。前种方法成本低,性能不比后种差, 但控制程序较复杂, 是未来的发展方向, 比如上海正艺科技的恒压供水控制系统就可实现一变频器控制任意数马达的功能。下面讲到的原理都是一变频器拖动多马达的系统。

三、 PID 控制原理

根据反馈原理:要想维持一个物理量不变或基本不变,就应该引这个物理量与恒值比较, 形成闭环系统。我们要想保持水压的恒定, 因此就必须引入水压反馈值与给定值比较, 从而形成闭环系统。但被控制的系统特点是非线性、大惯性的系统, 现在控制和 PID 相结合的方法, 在压力波动较大时使用模糊控制, 以加快响应速度; 在压力范围较小时采用 PID 来保持静态精度。这通过 PLC 加智能仪表可时现该算法, 同时对 PLC 的编程来时现泵的工频与变频之间的切换。实践证明,使用这种方法是可行的,而且造价也不高。

四、变频控制原理

用变频调速来实现恒压供水, 与用调节阀门来实现恒压供水相比, 节能效果十分显著(可根据具体情况计算出来) 。其优点是:

1、起动平衡, 起动电流可限制在额定电流以内, 从而避免了起动时对电网的冲击;

2、由于泵的平均转速降低了,从而可延长泵和阀门等的使用寿命;

3、可以消除起动和停机时的水锤效应;

一般地说,当由一台变频器控制一台电动机时,只需使变频器的配用电动机容量与实际电动机容量相符即可。当一台变频器同时控制两台电动机时, 原则上变频器的配用电动机容量应等于两台电动机的容量之和。但如在高峰负载时的用水量比两台水泵全速供水量相差很多时, 上海正艺科技的工程师建议, 可考虑适当减小变频器的容量,但应注意留有足够的容量。

虽然水泵在低速运行时, 电动机的工作电流较小。但是, 当用户的用水量变化频繁时,电动机将处于频繁的升、降速状态,而升、降速的电流可略超过电动机的额定电流,导致电动机过热。因此,电动机的热保护是必需的。对于这种由于频繁地升、降速而积累起来的温升, 变频器内的电子热保护功能是难以起到保护作用的,所以应采用热继电器来进行电动机的热保护。

在主要功能预置方面,最高频率应以电动机的额定频率为变频器的最高工作频率。升、降速时间在采用 PID 调节器的情况下,升、降速时间应尽量设定得短一些,以免影响由 PID 调节器决定的动态响应过程。如变频器本身具有 PID 调节功能时, 只要在预置时设定 PID 功能有效, 则所设定的升速和降速时间将自动失效。

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